A Reconfigurable Memory based Fast VLSI Architecture for Histogram Computation

Reconfigurable VLSI Architecture for FFT Processor

This paper presents a reusable intellectual property (IP) Coordinate Rotation Digital Computer (CORDIC)-based split-radix fast Fourier transform (FFT) core for orthogonal frequency division multiplexer (OFDM) systems, for example, Ultra Wide Band (UWB), Asymmetric Digital Subscriber Line (ADSL), Digital Audio Broadcasting (DAB), Digital Video Broadcasting – Terrestrial (DVB-T), Very High Bitrat...

Implementation of VlSI Based Image Compression Approach on Reconfigurable Computing System - A Survey

Image data require huge amounts of disk space and large bandwidths for transmission. Hence, imagecompression is necessary to reduce the amount of data required to represent a digital image. Thereforean efficient technique for image compression is highly pushed to demand. Although, lots of compressiontechniques are available, but the technique which is faster, memory efficient and simple, surely...

VLSI Architecture for Fast Memetic Vector Quantizer Design on Reconfigurable Hardware

A novel hardware architecture for memetic vector quantizer (VQ) design is presented in this paper. The architecture uses steady-state genetic algorithm (GA) for global search, and C-means algorithm for local refinement. It adopts a shift register based circuit for accelerating mutation and crossover operations for steady state GA operations. It also uses a pipeline architecture for the hardware...

A Configurable Architecture for Fast Moments Computation

VLSI Architecture for Hierarchical Temporal Memory

A large number of real world applications, such as image recognition and understanding, can still not be performed easily by conventional algorithms in comparison with the human brain. Implementing applications that require such intelligence, might therefore require a different approach, for which Hierarhical Temporal Memory (HTM) seems a promising framework. Currently HTM exists as a software ...